PLL Model for Grid Voltage Reference Reconstruction

Abstract

In power electronics area, the PLL (Phase Lock Loop) circuit is needed to reconstruct the sinusoidal reference signal used on the APF (active power filters) or grid-tied inverters, starting from the distorted grid voltage. Research area of the APF focuses more on the current of voltage control loops and less on the sinusoidal reference signal, usually considered available by default. Implementing in practice such a circuit poses difficulties since the available PLL integrated circuits are designed for digital telecommunication area, where signals are digital and a small phase error is acceptable. This paper presents a phase lock loop model with harmonic output and zero phase error during normal use.