Dual Priority Scheduling Algorithm Used in the nMPRA Microcontrollers – Dynamic Scheduler
Keywords:
real time system, dynamic hardware scheduler, microcontroller, pipeline processor
Abstract
This paper is a follow up of an already published paper that described the static scheduler. It deals with a true dynamic scheduling algorithm that is meant to maximize the CPU utilization. The dual priority algorithm is composed of two different scheduling algorithms, earliest deadline first (EDF) and round robin (RR). We have chosen EDF, because it is a dynamic scheduling algorithm, used in real time operating systems, which can be easily implemented in hardware, by improving the nHSE architecture. The new dynamic scheduler algorithm provides a much better CPU utilization, very good switching time for tasks and events within 5 to 8 machine cycles and guarantees that no task will suffer from starvation.
Downloads
Download data is not yet available.
References
[1]. Robert I. Davis, A review of fixed priority and EDF scheduling for hard real-time uniprocessor systems, Real-Time Systems Research Group, Department of Compuyter Science, University of York, York, UK.
[2]. Davis R. I., Burns A., Walker W., Guaranteeing Timing Constraints Under Shortest Remaining Processing Time Scheduling. In proceedings of the Euromicro Workshop on Real - Time Systems, p. 88-93, 1997.
[3]. Shaohua Teng, Wei Zhang, Haibin Zhu, Xiufen Fu, Jiangyi Su, Baoliang Cui, A Least-Laxity-First Scheduling Algorithm of Variable Time Slice for Periodic Tasks, International Journal of Software Science and Computational Intelligence, Vol. 2, Issue 2, April 2010.
[4]. Lucian Andries, Vasile Gheorghita Gaitan, Dual Priority Scheduling algorithm used in the nMPRA Microcontrollers, 18th International Conference on System Theory, Control and Computing, Sinaia, Romania, October 17-19, 2015.
[5]. Lucian Andries, Vasile Gheorghita Gaitan, Detailed Microcontroller Architecture based on a Hardware Scheduler Engine and Independent Pipeline Registers, 19th International Conference on System Theory, Control and Computing, Sinaia, Romania, October 17-19, 2014, ISBN 978-1-4799-4602-0, 2014.
[6]. Dodiu E., Gaitan V. G., Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – concept and theory of operation, IEEE EIT International Conference on Electro-Information Technology, Indianapolis, IN, USA, 6-8 May 2012.
[7]. Dodiu E., Gaitan V. G., Graur A., Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – architecture description, IEEE 35th Jubilee International Convention on Information and Communication Technology, Electronics and Microelectronics, Croatia, May 2012.
[8]. Gaitan V. G., Gaitan N. C., Ungurean I., CPU Arhitecture based on a Hardware Scheduler and Independent Pipeline Registers, IEEE Transactions on VLSI System, 2014, ISSN :1063- 8210.
[9]. Gaitan N., Lucian A., Using Dual Priority Scheduling to Improve the Resource Utilization in the nMPRA Microcontrollers, IEEE 12th International Conference on Development and Application Systems, Suceava, Romania, May 15-17, 2014.
[2]. Davis R. I., Burns A., Walker W., Guaranteeing Timing Constraints Under Shortest Remaining Processing Time Scheduling. In proceedings of the Euromicro Workshop on Real - Time Systems, p. 88-93, 1997.
[3]. Shaohua Teng, Wei Zhang, Haibin Zhu, Xiufen Fu, Jiangyi Su, Baoliang Cui, A Least-Laxity-First Scheduling Algorithm of Variable Time Slice for Periodic Tasks, International Journal of Software Science and Computational Intelligence, Vol. 2, Issue 2, April 2010.
[4]. Lucian Andries, Vasile Gheorghita Gaitan, Dual Priority Scheduling algorithm used in the nMPRA Microcontrollers, 18th International Conference on System Theory, Control and Computing, Sinaia, Romania, October 17-19, 2015.
[5]. Lucian Andries, Vasile Gheorghita Gaitan, Detailed Microcontroller Architecture based on a Hardware Scheduler Engine and Independent Pipeline Registers, 19th International Conference on System Theory, Control and Computing, Sinaia, Romania, October 17-19, 2014, ISBN 978-1-4799-4602-0, 2014.
[6]. Dodiu E., Gaitan V. G., Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – concept and theory of operation, IEEE EIT International Conference on Electro-Information Technology, Indianapolis, IN, USA, 6-8 May 2012.
[7]. Dodiu E., Gaitan V. G., Graur A., Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – architecture description, IEEE 35th Jubilee International Convention on Information and Communication Technology, Electronics and Microelectronics, Croatia, May 2012.
[8]. Gaitan V. G., Gaitan N. C., Ungurean I., CPU Arhitecture based on a Hardware Scheduler and Independent Pipeline Registers, IEEE Transactions on VLSI System, 2014, ISSN :1063- 8210.
[9]. Gaitan N., Lucian A., Using Dual Priority Scheduling to Improve the Resource Utilization in the nMPRA Microcontrollers, IEEE 12th International Conference on Development and Application Systems, Suceava, Romania, May 15-17, 2014.
Published
2015-06-15
How to Cite
1.
ANDRIEȘ L, GĂITAN VG. Dual Priority Scheduling Algorithm Used in the nMPRA Microcontrollers – Dynamic Scheduler. The Annals of “Dunarea de Jos” University of Galati. Fascicle IX, Metallurgy and Materials Science [Internet]. 15Jun.2015 [cited 5Nov.2024];38(2):66-1. Available from: https://gup.ugal.ro/ugaljournals/index.php/mms/article/view/1359
Issue
Section
Articles
